1. Field of the Invention
The present invention relates to a process for fabricating a metal silicide layer by using ion metal plasma deposition, and more particularly to a process for fabricating a metal silicide layer which alleviates the bridging effect.
2. Description of the Prior Art
The continued miniaturization of integrated circuits has brought about an increasing need to reduce the sheet resistance in the source/drain and gate regions. In metal-oxide-semiconductor (MOS) device manufacturing, self-aligned metal silicide layers (also known as "salicide" layers) have been used in reducing the sheet resistance of the source/drain and gate regions.
FIGS. 1A-1F show cross-sectional views illustrating the process flow of fabricating the metal salicide according to a conventional process. Referring to FIG. 1A, an oxide layer 11a and a polysilicon layer 12a are successively formed on a semiconductor substrate 10. Then, referring to FIG. 1B, the oxide layer 11a and the polysilicon layer 12a are patterned by photolithography and etching to form a gate region 13 including the patterned oxide layer 11 and the patterned polysilicon layer 12. Then, lightly-doped source and drain regions 22 are formed using a conventional ion implant method 20 using the gate region 13 as a doping mask.
Subsequently, referring to FIG. 1C, a dielectric layer is formed over the gate region 13 and the source/drain regions 22, and then anisotropically etched using reactive ion etching (RIE) to form a spacer 14 on the sidewall of the gate region 13.
Subsequently, referring to FIG. 1D, a heavily-doped source and drain regions 32 are formed using a conventional ion implant method 30 using the gate region 13 and the spacer 14 as a doping mask. Thus, source/drain regions 40 with a lightly doped drain (LDD) structure 22 is thus formed.
Subsequently, referring to FIG. 1E, a metal layer 50 is formed over the structure depicted in FIG. 1D. Referring then to FIG. 1F, a rapid thermal process (RTP) is then performed to make the metal layer 50 react with the silicon of the polysilicon layer 12 and the source/drain regions 40 to form a metal silicide layer 52 on both the polysilicon layer 12 and the source/drain regions 40, leaving the metal layer on the spacer substantially intact. Thus, a self-aligned metal silicide layer (also known as "salicide" layer) is formed. The metal layer 50 which did not react with silicon completely is then removed by wet etching.
One purpose of the spacer 14 is to separate the polysilicon layer 12 and the source/drain regions 40. However, in the above method, some silicon particles of the substrate 10 are very likely to diffuse onto the spacer 14 during the rapid thermal process, which react with the metal and form unwanted metal silicide on the spacer 14. This unwanted metal silicide can cause the polysilicon layer 12 to be undesirable short circuited to the source/drain regions 40. This conditions is referred to as "bridging effect".